PIPELINE IMPLEMENTATION OF THE 128-BIT BLOCK CIPHER CLEFIA IN FPGA

被引：11

作者：

Kryjak, Tomasz ^{[1
]}

Gorgon, Marek ^{[1
]}

机构：

[1] AGH Univ Sci & Technol, Dept Automat, Krakow, Poland

来源：

FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS | 2009年

关键词：

D O I：

10.1109/FPL.2009.5272264

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

The article presents a pipeline implementation of the block cipher CLEFIA. The article examines three known methods of implementing a single encryption round and proposes a new fourth method. The article proposes the implementation of a key scheduler, which is highly compatible with pipeline encryption. The article contains a detailed analysis of the data processing path for the 128-bit key version of the algorithm and verifies its operation on two FPGA cards in practice. On the basis of one of these cards, the article proposes a prototype of an effective supercomputer-compatible hardware accelerator (High Performance Computing Application).

引用

页码：373 / 378

页数：6

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