共 28 条
- [21] Flags and algebra for sequential circuit VNR path delay fault test generation TENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1997, : 88 - 94
- [22] SEESIM - A FAST SYNCHRONOUS SEQUENTIAL-CIRCUIT FAULT SIMULATOR WITH SINGLE-EVENT EQUIVALENCE IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS, 1993, 140 (02): : 101 - 105
- [23] BOUNDARY-SCAN PLUS IN-CIRCUIT TEST TO ACHIEVE MAXIMUM FAULT COVERAGE ELECTRONIC ENGINEERING, 1993, 65 (804): : 37 - 38
- [24] Generating all test patterns for a given stuck-at fault of a logical circuit and its ROBDD implementation VESTNIK TOMSKOGO GOSUDARSTVENNOGO UNIVERSITETA-UPRAVLENIE VYCHISLITELNAJA TEHNIKA I INFORMATIKA-TOMSK STATE UNIVERSITY JOURNAL OF CONTROL AND COMPUTER SCIENCE, 2014, 27 (02): : 82 - 89
- [25] A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2010, E93D (01): : 24 - 32
- [26] On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuits IEEE EUROPEAN TEST WORKSHOP, PROCEEDINGS, 2000, : 144 - 149
- [27] High fault coverage of in-circuit IC pin faults with a vectorless test technique using parasitic transistors INTERNATIONAL TEST CONFERENCE 1996, PROCEEDINGS, 1996, : 926 - 926