A two-level directory architecture for highly scalable cc-NUMA multiprocessors

被引:27
|
作者
Acacio, ME
González, J
García, JM
Duato, J
机构
[1] Univ Murcia, Dept Ingn & Tecnol Comp, Fac Informat, E-30071 Murcia, Spain
[2] Intel Labs Barcelona, Intel Barcelona Res Ctr, Barcelona 08034, Spain
[3] Univ Politecn Valencia, Dept Informat Sistemas & Comp, Valencia 46010, Spain
关键词
scalability; directory memory overhead; two-level directory architecture; compressed sharing codes; unnecessary coherence messages; cc-NUMA multiprocessor;
D O I
10.1109/TPDS.2005.4
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
One important issue the designer of a scalable shared-memory multiprocessor must deal with is the amount of extra memory required to store the directory information. It is desirable that the directory memory overhead be kept as low as possible, and that it scales very slowly with the size of the machine. Unfortunately, current directory architectures provide scalability at the expense of performance. This work presents a scalable directory architecture that significantly reduces the size of the directory for large-scale configurations of a multiprocessor without degrading performance. First, we propose multilayer clustering as an effective approach to reduce the width of directory entries. Based on this concept, we derive three new compressed sharing codes, some of them with a space complexity of O(log(2)(log(2)(N))) for an N-node system. Then, we present a novel two-level directory architecture to eliminate the penalty caused by compressed directories in general. The proposed organization consists of a small full-map first-level directory (which provides precise information for the most recently referenced lines) and a compressed second-level directory (which provides in-excess information for all the lines). The proposals are evaluated based on extensive execution-driven simulations (using RSIM) of a 64-node cc-NUMA multiprocessor. Results demonstrate that a system with a two-level directory architecture achieves the same performance as a multiprocessor with a big and nonscalable full-map directory, with a very significant reduction of the memory overhead.
引用
收藏
页码:67 / 79
页数:13
相关论文
共 50 条
  • [31] Utilization of the on-chip L2 cache area in CC-NUMA multiprocessors for applications with a small working set
    Chung, SW
    Kim, HS
    Jhon, CS
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2004, E87D (07): : 1617 - 1624
  • [32] Broadcast directory: A scalable cache coherent architecture for mesh-connected multiprocessors
    Rhee, Y
    Lee, J
    JOURNAL OF SYSTEMS ARCHITECTURE, 2000, 46 (10) : 903 - 918
  • [33] Two-level directory based compression
    Skibinski, P
    DCC 2005: DATA COMPRESSION CONFERENCE, PROCEEDINGS, 2005, : 481 - 481
  • [34] Performance evaluation of low level multithreaded BLAS kernels on intel processor based cc-NUMA systems
    Nishida, A
    Oyanagi, Y
    HIGH PERFORMANCE COMPUTING, 2003, 2858 : 500 - 510
  • [35] A software architecture of two-level parallelization
    Xu, CW
    Yang, DL
    INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS I-III, PROCEEDINGS, 1997, : 136 - 139
  • [36] QUKU: A two-level reconfigurable architecture
    Shukla, Sunil
    Bergmann, Neil W.
    Becker, Jurgen
    IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES, 2006, : 109 - +
  • [37] Two-level tiling for MPSoC architecture
    Bouchebaba, Youcef
    Bensoudane, Essaid
    Lavigueur, Bruno
    Paulin, Pierre
    Nicolescu, Gabriela
    2007 IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES, AND PROCESSORS, 2007, : 314 - 319
  • [38] System design of a CC-NUMA multiprocessor architecture using formal specification, model-checking, co-simulation, and test generation
    Garavel H.
    Viho C.
    Zendri M.
    International Journal on Software Tools for Technology Transfer, 2001, 3 (03) : 314 - 331
  • [39] A two-level interleaving architecture for serial convolvers
    Marino, F
    IEEE TRANSACTIONS ON SIGNAL PROCESSING, 1999, 47 (05) : 1481 - 1486
  • [40] Computational advantages of a two-level hybrid control architecture
    Moor, T
    Raisch, J
    Davoren, JM
    PROCEEDINGS OF THE 40TH IEEE CONFERENCE ON DECISION AND CONTROL, VOLS 1-5, 2001, : 358 - 363