RRAM for Compute-in-Memory: From Inference to Training

被引:68
|
作者
Yu, Shimeng [1 ]
Shim, Wonbo [1 ]
Peng, Xiaochen [1 ]
Luo, Yandong [1 ]
机构
[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA
基金
美国国家科学基金会;
关键词
Computer architecture; Training; Resistance; Microprocessors; Random access memory; Arrays; Reliability; Non-volatile memory; in-memory computing; deep neural network; hardware accelerator; MONOLITHICALLY INTEGRATED RRAM; NEURAL-NETWORKS; NONVOLATILE; PRECISION; EFFICIENT; SCHEME; MACRO; CMOS; READ;
D O I
10.1109/TCSI.2021.3072200
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
To efficiently deploy machine learning applications to the edge, compute-in-memory (CIM) based hardware accelerator is a promising solution with improved throughput and energy efficiency. Instant-on inference is further enabled by emerging non-volatile memory technologies such as resistive random access memory (RRAM). This paper reviews the recent progresses of the RRAM based CIM accelerator design. First, the multilevel states RRAM characteristics are measured from a test vehicle to examine the key device properties for inference. Second, a benchmark is performed to study the scalability of the RRAM CIM inference engine and the feasibility towards monolithic 3D integration that stacks RRAM arrays on top of advanced logic process node. Third, grand challenges associated with in-situ training are presented. To support accurate and fast in-situ training and enable subsequent inference in an integrated platform, a hybrid precision synapse that combines RRAM with volatile memory (e.g. capacitor) is designed and evaluated at system-level. Prospects and future research needs are discussed.
引用
收藏
页码:2753 / 2765
页数:13
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