ManArray processor interconnection network: An introduction

被引：0
|
作者：
Pechanek, GG [1 ]
Vassiliadis, S
Pitsianis, N
机构：
[1] Billions Operat Per Second Inc, Chapel Hill, NC USA
[2] Delft Univ Technol, Dept Elect Engn, Delft, Netherlands
[3] Duke Univ, Dept Comp Sci, Chapel Hill, NC USA
来源：
EURO-PAR'99: PARALLEL PROCESSING | 1999年 / 1685卷
关键词：
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
The present paper introduces the new interconnection network of the POPS ManArray family of available core products. To form a ManArray network, the processing elements are completely connected within clusters and communicate with members of only two other clusters thereby reducing signal fan-out and wiring density. With this simple network, single-step communications between a hypercube and its compliment node, single-step transpose operations, and a diameter of 2 are achieved.
引用
收藏
页码：761 / 765
页数：5
相关论文
共 50 条
  • [1] The ManArray™ embedded processor architecture
    Pechanek, GG
    Vassiliadis, S
    PROCEEDINGS OF THE 26TH EUROMICRO CONFERENCE, VOLS I AND II, 2000, : 348 - 355
  • [2] INTERCONNECTION NETWORK FOR MULTI-PROCESSOR COMPUTERS.
    Anon
    IBM technical disclosure bulletin, 1985, 28 (06):
  • [3] SPRINT - THE SYSTOLIC PROCESSOR WITH A RECONFIGURABLE INTERCONNECTION NETWORK OF TRANSPUTERS
    DEGROOT, AJ
    JOHANSSON, EM
    FITCH, JP
    GRANT, CW
    PARKER, SR
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1987, 34 (04) : 873 - 877
  • [4] Interconnection network analysis for a compliant massively parallel processor
    Perdue, DB
    Tabak, D
    JOURNAL OF SYSTEMS ARCHITECTURE, 1997, 42 (9-10) : 665 - 678
  • [5] NETWORK INTERCONNECTION - GUEST EDITORS INTRODUCTION
    FREEMAN, HA
    COMPUTER, 1983, 16 (09) : 11 - 13
  • [6] A new hierarchical interconnection network for multi-core processor
    Qiao, Baojun
    Shi, Feng
    Ji, Weixing
    ICIEA 2007: 2ND IEEE CONFERENCE ON INDUSTRIAL ELECTRONICS AND APPLICATIONS, VOLS 1-4, PROCEEDINGS, 2007, : 246 - 250
  • [7] PROCESSOR INTERCONNECTION STRATEGIES
    FINKEL, RA
    SOLOMON, MH
    IEEE TRANSACTIONS ON COMPUTERS, 1980, 29 (05) : 360 - 371
  • [8] New on-chip interconnection network for multi-core processor
    Qiao, Bao-Jun
    Shi, Feng
    Ji, Wei-Xing
    Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology, 2007, 27 (06): : 511 - 516
  • [9] Tutorial: Introduction to Interconnection Networks - From System Area Network to Network on Chips -
    Amano, Hideharu
    2013 FIRST INTERNATIONAL SYMPOSIUM ON COMPUTING AND NETWORKING (CANDAR), 2013, : 15 - 16
  • [10] A cost effective interconnection network for reconfigurable computing processor in digital signal processing applications
    Lai, Yeong-Kang
    Chen, Lien-Fei
    Chen, Jian-Chou
    Chiu, Chun-Wei
    IEICE TRANSACTIONS ON ELECTRONICS, 2006, E89C (11): : 1674 - 1675
12345