Near void free hybrid no-flow underfill flip chip process technology

被引:7
|
作者
Colella, M [1 ]
Baldwin, D [1 ]
机构
[1] Georgia Inst Technol, George W Woodruff Sch Mech Engn, Adv Assembly Proc Technol AdAPT Lab, Atlanta, GA 30332 USA
关键词
no-flow underfill; area array; flip chip; process optimization; void free; electronics packaging;
D O I
10.1109/ECTC.2004.1319426
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a systematic development of optimal no flow process underfill parameters compatible with four commercially available fluxing underfills. A novel hybrid process was developed that combines a capillary flow dynamic with no-flow fluxing underfills. The impact of the dispensing pattern on void formation is determined. Experiments are conducted to investigate the dispense pattern, placement speed and the impact of the placement process on interconnect yield further investigating the dispense pattern, placement force, and dwell time. A dispensed line pattern location and chip placement study is conducted to determine how voiding is affected by the position of the dispensed line in relation to the side of the die. The results of these experimental studies are used to select an optimal placement process for the materials. Reflow profile parameters are investigated using a parametric approach. The results of these initial studies are used to choose an optimal process for the materials. Test boards are assembled according to the optimal process for each material, and air to air thermal cycle, AATC, thermal cycling test is performed to qualify the assemblies. The newly developed edge patterned hybrid no-flow process has resulted in near void-free assemblies capable of passing 2000 cycles without an electrical failure for the -40 to 125 degreesC AATC reliability test.
引用
收藏
页码:780 / 788
页数:9
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