Scaling study of Si/SiGe MODFETs for RF applications

被引：1

作者：

Yang, L ^{[1
]}

Watling, JR ^{[1
]}

Wilkins, RCW ^{[1
]}

Asenov, A ^{[1
]}

Barker, JR ^{[1
]}

Roy, S ^{[1
]}

Hackbarth, T ^{[1
]}

机构：

[1] Univ Glasgow, Dept Elect & Elect Engn, Device Modelling Grp, Glasgow G12 8LT, Lanark, Scotland

来源：

EDMO 2002: 10TH IEEE INTERNATIONAL SYMPOSIUM ON ELECTRON DEVICES FOR MICROWAVE AND OPTOELECTRONIC APPLICATIONS | 2002年

关键词：

D O I：

10.1109/EDMO.2002.1174938

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Based on the successful calibration on a 0.25mum strained Si/SiGe n-type MODFET, this paper presents a gate length scaling study of double-side doped Si/SiGe MODFETs. Our simulations show that gate length scaling improves device RF performance. However, the short channel effects (SCE) along with the parasitic delays limit the device performance improvements. We find that it is necessary to consider scaling (dimensions and doping) of both the lateral and vertical architecture in order to optimize the device design.

引用

页码：101 / 106

页数：6

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