Development of vertical and tapered via etch for 3D through wafer interconnect technology

Two types of dry silicon etch techniques are developed to cover two different areas of demand for interconnect technology: one for high aspect ratio (AR) vertical vias and one for tapered vias. Various sizes of vertical vias and trenches with diameters/widths ranging from 1-100 mu m with an AR up to 50 are realized using Bosch Deep Reactive Ion Etch (DRIE) process. A linear model is applied to describe and to give physical insight in the Aspect Ratio Dependant Etch (ARDE) effect. The feasibility of the vertical vias as electrical interconnect is shown by isolating them from the substrate by silicon oxide and then filling with polysilicon. The tapered vias are typically post-processed on fabricated device wafers, making it inherently a more generic approach where diameter size can be large and low AR can be tolerated. Vias with a depth of similar to 100 mu m and a diameter of similar to 50 mu m at the bottom (though larger at top) are realized. Varying various etch parameters, slope angles of 70 degrees-80 degrees are realized to allow for conformal deposition of dielectric/seed materials on the sidewalls and to allow lithography within the via. Reactive Ion Etch (RIE) is used to fabricate sloped vias by simultaneously applying etch and passivation gasses. Negative angles on the via top and sidewall roughness are observed that introduce conformal coating problems and increased leakage currents. Smoothening techniques using maskless wet and dry silicon etching are investigated to overcome these problems.