Diagnostic simulation of sequential circuits using fault sampling

被引：0
|
作者：
Venkataraman, S [1 ]
Fuchs, WK [1 ]
Patel, JH [1 ]
机构：
[1] Univ Illinois, Coordinated Sci Lab, Urbana, IL 61801 USA
来源：
ELEVENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 1997年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes a technique to accelerate diagnostic fault simulation of sequential circuits using fault sampling. Diagnostic fault simulation involves computing the indistinguishability relationship between all pairs of modeled faults. The input space is the set of all pairs of modeled faults, thus making the simulation computationally intensive. The diagnostic simulation process is accelerated by considering a sub-space of the input space that is obtained using fault sampling. Results on performance speedup and diagnostic resolution loss are provided for the ISCAS 89 benchmark circuits.
引用
收藏
页码：476 / 481
页数：6
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