Cellular neural network based VLSI architecture for image processing

被引：0
|
作者：
Slot, K
Kowalski, J
Pacholik, J
Debiec, P
机构：
来源：
1996 FOURTH IEEE INTERNATIONAL WORKSHOP ON CELLULAR NEURAL NETWORKS AND THEIR APPLICATIONS, PROCEEDINGS (CNNA-96) | 1996年
关键词：
D O I：
10.1109/CNNA.1996.566569
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
The paper presents a way for increasing a size of images which can be processed using Cellular Neural Networks based VLSI circuits. Basic idea is to reduce a number of rows which are being simultaneously processed in a network. To verify the proposed ideal a VLSI integrated circuit which allows for realizing selected gray-level image analyses, has been designed, manufactured and its performance was examined. In addition, a possibility of applying the proposed concept in realizing image processing operations where global signal propagation is crucial such as e.g. halftoning, have been discussed.
引用
收藏
页码：249 / 254
页数：6
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