The circuits and robust design methodology of the massively parallel processor based on the matrix architecture

被引：3

作者：

Noda, Hideyuki ^{[1
]}

Tanizaki, Tetsushi ^{[1
]}

Gyohten, Takayuki ^{[1
]}

Dosaka, Katsumi ^{[1
]}

Nakajima, Masami ^{[1
]}

Mizumoto, Katsuya ^{[1
]}

Yoshida, Kanako ^{[1
]}

Iwao, Takenobu ^{[1
]}

Nishijima, Tetsu ^{[1
]}

Okuno, Yoshihiro ^{[1
]}

Arimoto, Kazutami ^{[1
]}

机构：

[1] Renesas Technol Corp, Itami, Hyogo 6640005, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2007年 / 42卷 / 04期

关键词：

CMOS; integrated circuits; low power; memory; parallel processor; SIMD;

D O I：

10.1109/JSSC.2007.891680

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Novel circuits and design methodology of the massively parallel processor based on the matrix architecture are introduced. A fine-grained processing elements (PE) circuit for high-throughput MAC operations based on the Booth's algorithm enhances the performance of a 16-bit fixed-point signed MAC, which operates up to 30.0 GOPS/W. The dedicated I/O interface circuits are designed for converting the direction of data access and supporting the interleaved memory architecture, and they are implemented for maximizing the processor core efficiency. Power management techniques for suppressing current peaks and reducing average power consumption are proposed to enhance the robustness of the macro. The circuits and the design methodology proposal in this paper are attractive for achieving a high performance and robust massively parallel SIMD processor core employed in multimedia SoCs.

引用

页码：804 / 812

页数：9

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