A SDR Architecture based on FPGA for Multi-standard Transmitter

This paper presents the architecture and implementation of configurable base-band transmitter for software defined radio system. The proposed architecture is capable of generating data-frames for multiple communications standards. The radio parameters can be adjusted on-the-fly: length of data frame, training scheme, transmitter rate, upsampling factor, modulation type and pulse-shaping filter waveform. The configuration is carried out through an interface module via control words. Additionally, it is possible to operate in both continuous and burst data flow. The architecture was described using Verilog HDL and targeted in Altera Stratix V: 5SGXMA7N1F45C1. The implementation results show a reduced consumption of FPGA resources (<= 1 %) and frequency operation over 224 MHz.