An Interconnection Architecture for Integrate and Fire Neuromorphic Multi-Chip Networks

被引：6

作者：

Sargeni, Fausto ^{[1
]}

Bonaiuto, Vincenzo ^{[1
]}

机构：

[1] Univ Roma Tor Vergata, Dept Elect Engn, Rome, Italy

来源：

2009 52ND IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 | 2009年

关键词：

D O I：

10.1109/MWSCAS.2009.5235906

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The availability of large neuromorphic electronic systems can represent a really useful tool to deeply and effectively investigate on innovative, "bio-inspired", computational paradigms. Among the others, one of the main obstacles in implementation of large networks is represented by the limited silicon area available on a chip that requires further efforts to design interconnected architectures. A particular strategy to reduce the I/O analogue pins well suited for neuromorphic multi chip architecture will be presented.

引用

页码：877 / 880

页数：4

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