Fully-depleted SOI-MOSFET model for circuit simulation and its application to 1/f noise analysis

被引：0

作者：

Sadachika, N ^{[1
]}

Uetsuji, Y ^{[1
]}

Kitamaru, D ^{[1
]}

Mattausch, HJ ^{[1
]}

Miura-Mattausch, M ^{[1
]}

Weiss, L ^{[1
]}

Feldmann, U ^{[1
]}

Baba, S ^{[1
]}

机构：

[1] Hiroshima Univ, Grad Sch Adv Sci Matter, Higashihiroshima 7398530, Japan

来源：

SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES 2004 | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have developed a fully-depleted SOI-MOSFET model HiSIM-SOI for circuit simulation by solving the potential distribution along all three important SOI-surfaces self-consistently. Besides comparison to measured I-V data, the model is verified with l If noise analysis, sensitive to the carrier concentration and distribution along the channel. The carrier concentration increase, due to confinement of the silicon layer, results in enhanced 1/f noise in comparison with the bulk-MOSFET. Our results show that further reduction of the silicon-layer thickness for achieving higher driving capability will cause unavoidable enhancement of the noise.

引用

页码：255 / 258

页数：4

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