Fully-depleted SOI-MOSFET model for circuit simulation and its application to 1/f noise analysis

被引：0

作者：

Sadachika, N ^{[1
]}

Uetsuji, Y ^{[1
]}

Kitamaru, D ^{[1
]}

Mattausch, HJ ^{[1
]}

Miura-Mattausch, M ^{[1
]}

Weiss, L ^{[1
]}

Feldmann, U ^{[1
]}

Baba, S ^{[1
]}

机构：

[1] Hiroshima Univ, Grad Sch Adv Sci Matter, Higashihiroshima 7398530, Japan

来源：

SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES 2004 | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have developed a fully-depleted SOI-MOSFET model HiSIM-SOI for circuit simulation by solving the potential distribution along all three important SOI-surfaces self-consistently. Besides comparison to measured I-V data, the model is verified with l If noise analysis, sensitive to the carrier concentration and distribution along the channel. The carrier concentration increase, due to confinement of the silicon layer, results in enhanced 1/f noise in comparison with the bulk-MOSFET. Our results show that further reduction of the silicon-layer thickness for achieving higher driving capability will cause unavoidable enhancement of the noise.

引用

页码：255 / 258

页数：4

共 50 条

[1] Investigation of veritcal graded channel doping in nanoscale fully-depleted SOI-MOSFET
Ramezani, Zeinab
Orouji, Ali A.
SUPERLATTICES AND MICROSTRUCTURES, 2016, 98 : 359 - 370
[2] Nonquasistatic transient model of fully-depleted SOI MOSFET and its application to the analysis of charge sharing in an analog switch
Dubois, E
Robilliart, E
IEEE ELECTRON DEVICE LETTERS, 2002, 23 (01) : 43 - 45
[3] Deep-submicrometre fully-depleted SOI MOSFET drain current model for digital/analogue circuit simulation
Hu, MC
Jang, SL
INTERNATIONAL JOURNAL OF ELECTRONICS, 1998, 84 (03) : 167 - 185
[4] Systematic yield simulation methodology applied to fully-depleted SOI MOSFET process
Miura, N
Hayashi, H
Fukuda, K
Nishi, K
IEICE TRANSACTIONS ON ELECTRONICS, 2000, E83C (08) : 1288 - 1294
[5] Accurate analytical drain current model for a nanoscale fully-depleted SOI MOSFET
Anvarifard, Mohammad K.
Orouji, Ali A.
SOLID-STATE ELECTRONICS, 2015, 103 : 154 - 161
[6] Threshold voltage model for a fully depleted SOI-MOSFET with a non-uniform profile
Zhang, Guohe
Shao, Zhibiao
Zhou, Kai
Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors, 2007, 28 (06): : 842 - 847
[7] Unified 1/f noise SOI MOSFET modelling for circuit simulation
Iniguez, B
Tambani, M
Dessard, V
Flandre, D
ELECTRONICS LETTERS, 1997, 33 (21) : 1781 - 1782
[8] New threshold voltage shift model due to radiation in fully-depleted SOI MOSFET
Wan, Xin-Heng
Zhang, Xing
Tan, Jing-Rong
Gao, Wen-Yu
Huang, Ru
Wang, Yang-Yuan
Tien Tzu Hsueh Pao/Acta Electronica Sinica, 2001, 29 (11): : 1519 - 1521
[9] HiSIM-SOI: SOI-MOSFET Model for Circuit Simulation Valid also for Device Optimization
Sadachika, N.
Kusu, S.
Ishimura, K.
Murakami, T.
Kajiwara, T.
Hayashi, T.
Nishikawa, Y.
Yoshida, T.
Miura-Mattausch, M.
NANOTECH CONFERENCE & EXPO 2009, VOL 3, TECHNICAL PROCEEDINGS, 2009, : 550 - 553
[10] Non-quasi-static physics-based circuit model of fully-depleted double-gate SOI MOSFET
Jankovic, N
Pesic, T
SOLID-STATE ELECTRONICS, 2005, 49 (07) : 1086 - 1089

← 1 2 3 4 5 →