A Dual Power Mode GaN Doherty Power Amplifier Based on Cascode Transistors

This letter presents a fully integrated dual power mode Doherty power amplifier (PA) in the Nanjing Electronic Devices Institute (NEDI) 250-nm GaN process. Due to the advantages of high power (HP) and gain, the cascode architecture is introduced to both carrier and peaking PAs. To the author's best knowledge, this is the first time cascode architecture is applied in GaN process for sub-6 GHz Doherty PA design. The equivalent parasitic network and interstage impedance matching network of cascode transistors are constructed and extracted within the frequency range of 1-15 GHz. High efficiency voltage-current waveform at the current generator plane of carrier PA is achieved. The gate and drain bias of the common gate transistor are adjusted to attain low power (LP)/HP mode. A Doherty PA prototype operating in 5G NR FR1 n78 is presented with a saturated power of 36.5-37.2 dBm, a peaking power added efficiency (PAE) of 49.6%-52.0%, a 6-dB back-off PAE of 34.4%-39.6%, and a gain of 12.2-12.9 dB for LP mode. The realized high-gain saturated power is 39.8-40.5 dBm with a relatively HP density of 3.96 W/mm, a peaking PAE of 42.5%-47.7%, a 6-dB back-off PAE of 32.0%-37.8%, and a gain of 16.0-16.4 dB for HP mode.