Routability and fault tolerance of FPGA interconnect architectures

被引：0
|
作者：
Huang, J [1 ]
Tahoori, MB [1 ]
Lombardi, F [1 ]
机构：
[1] Northeastern Univ, Dept Elect & Comp Engn, Boston, MA 02115 USA
来源：
INTERNATIONAL TEST CONFERENCE 2004, PROCEEDINGS | 2004年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a new approach for the evaluation of FPGA routing resources in the presence of interconnect faults. All possible interconnect faults for programmable switches and wiring channels are considered. Signal routing in the presence of faulty interconnect resources is analyzed at both switch block and the entire FPGA. Two new probabilistic routing (routability) metrics are proposed and used as figures of merit for evaluating the interconnect resources of commercially available FPGAs as well as academic architectures.
引用
收藏
页码：479 / 488
页数：10
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