共 50 条
- [22] Fast Decoder of BCH Code with Cyclic Decoding Method 2016 INTERNATIONAL SIBERIAN CONFERENCE ON CONTROL AND COMMUNICATIONS (SIBCON), 2016,
- [24] Parallel Decoding for Multi-Stage BCH decoder 2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2016, : 107 - 108
- [25] DECODER FOR DEC-TED BCH CODES. Transactions of the Institute of Electronics and Communication Engineers of Japan. Section E, 1984, E 67 (07): : 393 - 394
- [28] VLSI design of BCH decoder in NAND flash controller Zheng, Z. (zxzheng@hust.edu.cn), 1600, Huazhong University of Science and Technology (42):
- [30] VHDL implementation of a BCH minimum weight decoder for double error PROCEEDINGS OF THE EIGHTEENTH NATIONAL RADIO SCIENCE CONFERENCE, VOLS 1 AND 2, 2001, : 361 - 368