Performance Analysis of Dielectric Engineered Negative Capacitance Tunnel FETs

被引：0
|
作者：
Harikumar, K. R. [1 ]
Das, Midhun P. [1 ]
Shikha, U. S. [1 ]
James, Rekha K. [1 ]
Pradeep, Anju [1 ]
机构：
[1] CUSAT, Sch Engn, Kochi, Kerala, India
来源：
2022 IEEE 3RD INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURE, TECHNOLOGY AND APPLICATIONS, VLSI SATA | 2022年
关键词：
Double Gate; Negative Capacitance; Dielectric Engineering; Tunnel Field Effect Transistor;
D O I：
10.1109/VLSISATA54927.2022.10046624
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
The ability to amplify the gate voltage exists in ferroelectric (FE) materials in the negative capacitance (NC) domain. A simulation-based study of NC TFETs which has Si doped HfO2 as the FE material is included in this paper. A comparative study between low-k, high-k and combination of high-k over low-k is presented here to analyze the performance metrics such as ON current, subthreshold swing (SS) and ON-OFF current ratio. The numerical simulation is performed by combining one-dimensional (1-D) Landau-Khalatnikov (LK) equation and two-dimensional (2-D) TCAD. Based on published earlier studies, this study examines the idea of NC in TFET.
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页数：4
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