Design of multipliers for GF(2m)

被引：5
|
作者：
Mao, Z. [1 ]
Shou, G. [1 ]
Hu, Y. [1 ]
Guo, Z. [1 ]
机构：
[1] Beijing Univ Posts & Telecommun, Sch Informat & Commun Engn, Beijing 100876, Peoples R China
来源：
ELECTRONICS LETTERS | 2010年 / 46卷 / 06期
基金：
国家高技术研究发展计划(863计划);
关键词：
FINITE-FIELD MULTIPLIER; COMPLEXITY;
D O I：
10.1049/el.2010.0246
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new design of multipliers for GF(2(m)) based on combination of bit-serial and bit-parallel schemes with low complexity is proposed. Using pipeline architecture, the scheme yields significantly lower latency compared to known bit-parallel multipliers for GF(2(m)).
引用
收藏
页码：419 / U58
页数：2
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