A 0.18-μm 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)

被引：0
|
作者：
Cho, WY [1 ]
Cho, BH
Choi, BG
Oh, HR
Kang, SB
Kim, KS
Kim, KH
Kim, DE
Kwak, CK
Byun, HG
Hwang, Y
Ahn, SJ
Koh, GH
Jeong, G
Jeong, H
Kim, K
机构：
[1] Samsung Elect Co Ltd, Mem Div, SRAM Team, Hwasung City 445701, Gyeonggi Do, South Korea
[2] Samsung Elect Co Ltd, Mem Div, Technol Dev Team, Yongin, Gyeonggi Do, South Korea
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2005年 / 40卷 / 01期
关键词：
phase change; phase-transition random access memory (PRAM); RESET; SET;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A nonvolatile 64-Mb 1T1R phase-transition random access memory (PRAM) has been developed by fully integrating chalcogenied storage material (GST: Ge2Sb2Te5) into 0.18-mum CMOS technology. To optimize SET/RESET distribution, 512-kb sub-array core architecture was proposed, featuring meshed ground line and separated SET/RESET control schemes. Random read access time, random SET and RESET write access times were measured to be 60 ns, 120 ns, and 50 ns, respectively, at 3.0-V supply voltage with 30degreesC.
引用
收藏
页码：293 / 300
页数：8
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