Enhanced write performance of a 64-Mb phase-change random access memory

被引：44
|
作者：
Oh, HR [1 ]
Cho, BH
Cho, WY
Kang, S
Choi, BG
Kim, HJ
Kim, KS
Kim, DE
Kwak, CK
Byun, HG
Jeong, GT
Jeong, HS
Kim, K
机构：
[1] Samsung Elect Co Ltd, Memory Div, SRAM Team, Hwasung 445701, South Korea
[2] Samsung Elect Co Ltd, Technol Dev Team, Yongin 449711, South Korea
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2006年 / 41卷 / 01期
关键词：
distribution; phase change; PRAM; RESET; set;
D O I：
10.1109/JSSC.2005.859016
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The write performance of the 1.8-V 64-Mb phase-change random access memory (PRAM) has been improved, which was developed based on 0.12-mu m CMOS technology. For the improvement of RESET and SET distributions, a cell current regulator scheme and multiple step-down pulse generator were employed, respectively. The read access time and SET write time are 68 ns and 180 ns, respectively.
引用
收藏
页码：122 / 126
页数：5
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