A Four-Way Nested Digital Doherty Power Amplifier for Low-Power Applications

被引:4
|
作者
Sheth, Jay [1 ]
Bowers, Steven M. [1 ]
机构
[1] Univ Virginia, Dept Elect & Comp Engn, Charlottesville, VA 22903 USA
基金
美国国家科学基金会;
关键词
Compact matching network; complementary metal-oxide-semiconductor (CMOS); differential power amplifier (PA); digital Doherty; Internet of Things (IoT); low power; CMOS; EFFICIENCY; TRANSMITTER; DESIGN;
D O I
10.1109/TMTT.2021.3057895
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This article demonstrates the advantages of a nested digital Doherty power amplifier (PA) to achieve high efficiency in deep power hack-off (PBO) for low-power applications. A differential four-way digital Doherty PA (D4DPA) is implemented in a general-purpose 65-nm CMOS process as a proof-of-concept that ideally achieves efficiency enhancement through 9-dB PBO. The PA uses a compact input and output matching network through consolidation of components, and it achieves a peak drain efficiency (DE) of 48% and a system efficiency (SE) of 31% with 7.3 dBm of output power (P-out) and 14 dB of gain at 4.75 GHz. It also obtains a DE of 42% and 20% at 0- and 12.8-dB PBO, respectively, at 5.25 GHz, which corresponds to a 2.2x improvement over normalized class B PA. Finally, RF modulation measurements performed on the PA show that it achieves a DE of 34% and an rms error vector magnitude (EVMrms) of 20.5 dB for a 1-MSymis 16 QAM RF waveform at 5.25 GHz.
引用
收藏
页码:2782 / 2794
页数:13
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