An architecture and task scheduling algorithm for systems based on dynamically reconfigurable shared memory clusters

The paper presents proposals of a new architecture and respective task scheduling algorithms for a multi-processor system based on dynamically organised shared memory clusters. The clusters axe organised around memory modules placed in a common address space. Each memory module can be accessed through a local cluster bus and a common inter-cluster bus. Execution of tasks in a processor is done according to a specific macro dataflow model. It allows task execution only if all data needed by a task have been loaded into processor data cache. The data cache pre-fetching and single assignment data move principle enable elimination of cache thrashing and cache coherence problem. An extended macro dataflow graph representation is introduced that enables modelling of data bus arbiters, memory modules and data caches in the system. A task scheduling algorithm is proposed that defines mapping of program tasks into dynamic processor clusters on the basis of a program graph analysis. The algorithm is based on a modified Dominant Sequence Clustering approach and defines such dynamic structuring of clusters that minimises program execution time.