A background calibration scheme for pipelined ADCs including non-linear operational amplifier gain and reference error correction

This paper presents a background non-invasive true calibration technique to correct for non-idealities in pipelined Analog-to-Digital Converters (ADCs). Pipelined ADC suffers from finite non-linear gain in amplifiers, ratio mismatch in capacitors, and errors in voltage references. Most calibration schemes do not account for reference voltage errors or non-linearity in amplifiers, which introduce severe distortion in pipelined ADCs designed in a deep-submicron and nanometerscale digital CMOS process. The proposed digital calibration scheme uses an insignificant, low-speed, low-power, high-resolution Sigma-Delta ADC to estimate a set of digital error-correction parameters in background using an adaptive LMS algorithm. The technique will be shown to correct for all static errors within a single framework - finite amplifier gain, capacitor ratio mismatch, voltage reference errors and amplifier non-linearity. The scheme is demonstrated for a 14-bit A/D converter intended for speeds higher than 100Msample/s.