Variable-amplitude dither-based digital background calibration algorithm for linear and high-order nonlinear error in pipelined ADCs

被引：7
|
作者：
Yang, Shuo
Cheng, Jun [1 ]
Wang, Pei [1 ]
机构：
[1] Xi An Jiao Tong Univ, Sch Elect & Informat Engn, Xian 710049, Shaanxi, Peoples R China
来源：
MICROELECTRONICS JOURNAL | 2010年 / 41卷 / 07期
关键词：
Pipelined ADC; Digital background calibration; Variable-amplitude; Dither-based; Correlation-based;
D O I：
10.1016/j.mejo.2010.04.012
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Dither-based digital background calibration algorithm has been used to eliminate the influence of linear and nonlinear errors in pipelined ADC. However, this algorithm suffers from two disadvantages: too slow convergent speed and deduction of transmitting signal's amplitude in analog circuits due to dither injection. Input-dependent variable-amplitude dither-based algorithm is used in this paper to conquer both disadvantages. This proposed algorithm is implemented in a 14-bit, 100 MHz sample-rate pipelined ADC. The simulation results illustrate signal-to-noise and distortion (SINAD) of 76.56 dB after calibration of linear and nonlinear errors. Furthermore, the convergent speed is improved much more. (C) 2010 Elsevier Ltd. All rights reserved.
引用
收藏
页码：403 / 410
页数：8
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