A modular 0.13 μm bulk CMOS technology for high performance and low power applications

被引：37

作者：

Han, LK ^{[1
]}

Biesemans, S ^{[1
]}

Heidenreich, J ^{[1
]}

Houlihan, K ^{[1
]}

Lin, C ^{[1
]}

McGahay, V ^{[1
]}

Schiml, T ^{[1
]}

Schmidt, A ^{[1
]}

Schroeder, UP ^{[1
]}

Stetter, M ^{[1
]}

Wann, C ^{[1
]}

Warner, D ^{[1
]}

Mahnkopf, R ^{[1
]}

Chen, B ^{[1
]}

机构：

[1] IBM Corp, Microelect Div, Hopewell Junction, NY 12533 USA

来源：

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIT.2000.852749

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A leading-edge 0.13 mu m generation CMOS technology is presented as a platform for systems on a chip (SOC) applications. A modular triple gate oxide process concept is introduced for the first time to allow the optimization of high performance devices, low leakage devices, and I/O devices independently. Process commonality is also achieved to support deep-trench based embedded DRAM. Seven levels of Cu interconnects integrated with low-k ILD have been developed. With mature KrF 248 am lithography and optical enhancement techniques, aggressive design rules are achieved to meet the circuit density requirement. A 2.48 mu m(2) functional 6T-SRAM cell is demonstrated.

引用

页码：12 / 13

页数：2

共 50 条

[41] Total ionizing dose effects on the analog performance of a 0.13 μm CMOS technology
Re, V
Manghisoni, M
Ratti, L
Speziali, V
Traversi, G
NSREC: 2005 IEEE Radiation Effects Data Workshop, Workshop Record, 2005, : 122 - 126
[42] A 0.15 μm CMOS foundry technology with 0.1 μm devices for high performance applications
Diaz, CH
Chang, M
Chen, W
Chiang, M
Su, H
Chang, S
Lu, P
Hu, C
Pan, K
Yang, C
Chen, L
Su, C
Wu, C
Wang, CH
Wang, CC
Shih, J
Hsieh, H
Tao, H
Jang, S
Yu, M
Shue, S
Chen, B
Chang, T
Hou, C
Liew, BK
Lee, KW
Sun, YC
2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2000, : 146 - 147
[43] A High-Temperature Model of MOSFET Characteristics in 0.13-μm Bulk CMOS
Vosooghi, Bozorgmehr
Chen, Jinghong
2018 3RD IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS AND MICROSYSTEMS (ICICM), 2018, : 80 - 85
[44] A low power and high linearity UWB low noise amplifier (LNA) for 3.1-10.6 GHz wireless applications in 0.13 μm CMOS process
Rastegar, Habib
Saryazdi, Saeed
Hakimi, Ahmad
MICROELECTRONICS JOURNAL, 2013, 44 (03) : 201 - 209
[45] A CMOS 0.13μm Low Power Front-End for GEM detectors
Costantini, A.
Pezzotta, A.
Baschirotto, A.
De Matteis, M.
D'Amico, S.
Murtas, F.
Gorini, G.
2012 19TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2012, : 193 - 196
[46] Design of a high gain and power efficient optical receiver front-end in 0.13 M RF CMOS technology for 10 Gbps applications
Andre, Ponchet
Jacobus, Swart
MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 2016, 58 (06) : 1499 - 1504
[47] High-Speed, Radiation-Tolerant Laser Drivers in 0.13 μm CMOS Technology for HEP Applications
Mazza, Giovanni
Tavernier, Filip
Moreira, Paulo
Calvo, Daniela
De Remigis, Paolo
Olantera, Lauri
Soos, Csaba
Troska, Jan
Wyllie, Ken
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2014, 61 (06) : 3653 - 3659
[48] High ESD performance, low power CMOS LNA for GPS applications
Leroux, P
Vassilev, V
Steyaert, M
Maes, H
JOURNAL OF ELECTROSTATICS, 2003, 59 (3-4) : 179 - 192
[49] SYNCHRONOUS CMOS MEMORIES FOR HIGH PERFORMANCE, LOW POWER APPLICATIONS.
Young, Dennis C.
Technology Review, 1979,
[50] A 0.13 μm poly-SiGe gate CMOS technology for low-voltage mixed-signal applications
Ponomarev, YV
Stolk, PA
Dachs, CJJ
Montree, AH
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2000, 47 (07) : 1507 - 1513

← 1 2 3 4 5 →