Formal verification of globally-iterated and locally-non-iterated finite state machines

被引:0
|
作者
Ivanov, L [1 ]
Nunna, R [1 ]
机构
[1] Stevens Inst Technol, Dept Comp Sci, Hoboken, NJ 07030 USA
来源
42ND MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2 | 1999年
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Formal Verification of hardware has significantly gained in popularity as an alternative to testing and simulation in hardware design. Recently we introduced a new methodology for verification of non-iterated systems. The technique is based on the inductively defined notion of a series-parallel poser. In this paper we extend the notion of series-parallel posers to allow the modeling of systems involving global iteration. For this class of systems we present a verification algorithm, and discuss its foundation.
引用
收藏
页码:202 / 205
页数:4
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