共 50 条
- [31] Design and implementation of arithmetic processor F2155 for elliptic curve cryptosystems APCCAS '98 - IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS: MICROELECTRONICS AND INTEGRATING SYSTEMS, 1998, : 647 - 650
- [32] A novel high-speed parallel multiply-accumulate arithmetic architecture employing modified radix-4 signed-binary recoding PROCEEDINGS OF THE 39TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, 1996, : 57 - 60
- [33] EFFICIENT IMPLEMENTATION OF REGULAR PARALLEL ADDERS FOR BINARY SIGNED DIGIT NUMBER REPRESENTATIONS MICROPROCESSING AND MICROPROGRAMMING, 1992, 35 (1-5): : 319 - 326
- [34] High-speed hardware architecture of scalar multiplication for binary elliptic curve cryptosystems MICROELECTRONICS JOURNAL, 2016, 52 : 49 - 65
- [36] Design and implementation of arithmetic processor F2(155) for elliptic curve cryptosystems IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings, 1998, : 647 - 650
- [38] Parallel optical negabinary signed-digit computing: Algorithm and optical implementation Optical Engineering, 1999, 38 (1-3): : 403 - 414
- [40] Software implementation of elliptic curve cryptography over binary fields CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS-CHES 2000, PROCEEDINGS, 2001, 1965 : 1 - 24