System-level design of bacterial cell cycle control

被引:38
|
作者
McAdams, Harley H. [1 ]
Shapiro, Lucy [1 ]
机构
[1] Stanford Univ, Dept Dev Biol, Sch Med, Stanford, CA 94305 USA
关键词
Cell cycle; Cell regulation; Systems biology; Robustness; Cell biology; Caulobacter; CAULOBACTER-CRESCENTUS; DNA METHYLTRANSFERASE; PROTEASE COMPLEX; GENETIC CIRCUIT; REPLICATION; PROGRESSION; DIVISION; PROTEOBACTERIA; TRANSCRIPTION; ARCHITECTURE;
D O I
10.1016/j.febslet.2009.09.030
中图分类号
Q5 [生物化学]; Q7 [分子生物学];
学科分类号
071010 ; 081704 ;
摘要
Understanding of the cell cycle control logic in Caulobacter has progressed to the point where we now have an integrated view of the operation of an entire bacterial cell cycle system functioning as a state machine. Oscillating levels of a few temporally-controlled master regulator proteins in a cyclical circuit drive cell cycle progression. To a striking degree, the cell cycle regulation is a whole cell phenomenon. Phospho-signaling proteins and proteases dynamically deployed to specific locations on the cell wall are vital. An essential phospho-signaling system integral to the cell cycle circuitry is central to accomplishing asymmetric cell division. (c) 2009 Federation of European Biochemical Societies. Published by Elsevier B.V. All rights reserved.
引用
收藏
页码:3984 / 3991
页数:8
相关论文
共 50 条
  • [31] System-level control of structural hierarchy
    Macfarlane, Robert
    ABSTRACTS OF PAPERS OF THE AMERICAN CHEMICAL SOCIETY, 2019, 257
  • [32] Research of design for system-level testability and system partition
    Li, TG
    Huang, KL
    Lian, GY
    Wang, BL
    ICEMI 2005: Conference Proceedings of the Seventh International Conference on Electronic Measurement & Instruments, Vol 1, 2005, : 242 - 245
  • [33] System-level design of a readout circuit with thermostatic control for a MEMS pellistor sensor
    Leman, O.
    Srivastava, M.
    Hauer, J.
    2015 SYMPOSIUM ON DESIGN, TEST, INTEGRATION AND PACKAGING OF MEMS/MOEMS (DTIP), 2015,
  • [34] RISC VLSI DESIGN FOR SYSTEM-LEVEL PERFORMANCE
    ROWEN, C
    CRUDELE, L
    FREITAS, D
    HANSEN, C
    HUDSON, E
    KINSEL, J
    MOUSSOURIS, J
    PRZYBYLSKI, S
    RIORDAN, T
    VLSI SYSTEMS DESIGN, 1986, 7 (03): : 81 - &
  • [35] System-level design for nano-electronics
    Atienza, David
    Bobba, Shashi Kanth
    Poli, Massimo
    De Micheli, Giovanni
    Benini, Luca
    2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4, 2007, : 747 - +
  • [36] System-level design for partially reconfigurable hardware
    Qu, Yang
    Tiensyrja, Kari
    Soininen, Juha-Pekka
    Nurmi, Jari
    2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 2738 - +
  • [37] Design optimization with system-level reliability constraints
    McDonald, M.
    Mahadevan, S.
    JOURNAL OF MECHANICAL DESIGN, 2008, 130 (02)
  • [38] System-Level Design Optimization of a Hybrid Tug
    Hofman, T.
    Naaborg, M.
    Sciberras, E.
    2017 IEEE VEHICLE POWER AND PROPULSION CONFERENCE (VPPC), 2017,
  • [39] Coping With Variations Through System-level Design
    Banerjee, Nilanjan
    Chandra, Saumya
    Ghosh, Swaroop
    Dey, Sujit
    Raghunathan, Anand
    Roy, Kaushik
    22ND INTERNATIONAL CONFERENCE ON VLSI DESIGN HELD JOINTLY WITH 8TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, 2009, : 581 - +
  • [40] IP INTEGRATION: IS IT THE REAL SYSTEM-LEVEL DESIGN?
    Wilson, Ron
    EDN, 2010, 55 (15) : 34 - 40