Power Loop Inductance Extraction with High Order Polynomial Fitting Algorithm for SiC MOSFET Power Module Characterization

An accurate method for extracting the power loop parasitic inductance with high order polynomial fitting algorithm is proposed for SiC MOSFET power module characterization. Extracting power loop inductance of SiC MOSFET power module characterization is more difficult compared with IGBT power module due to higher switching speed. The relationship between the maximum di/dt and the voltage spike at turn-off transient is revealed. Compared with the four existing methods, high-order fitting method provides accuracy and repeatability. The calculated results are consistent with the Ansys Q3D simulation results. The fitted lines with the calculated stray inductance and di/dt match with the drain-tosource voltage of SiC MOSFET power module at both turn-on and turn-off transient. High-order fitting polynomial method is effective to extract the power loop inductance of SiC MOSFET power module characterization.