A 0.6-V, 74.2-dB DR Continuous-Time Sigma-Delta Modulator With Inverter-Based Amplifiers

被引：11
|
作者：
de Aguirre, Paulo Cesar C. [1 ,2 ]
Susin, Altamiro Amadeu [1 ]
机构：
[1] Univ Fed Rio Grande do Sul, Dept Elect Engn, BR-90035190 Porto Alegre, RS, Brazil
[2] Univ Fed Pampa, Campus Alegrete, BR-97546550 Alegrete, Brazil
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2018年 / 65卷 / 10期
关键词：
Sigma-delta modulator; continuous-time; inverter-based amplifier; low-voltage; single-amplifier resonator; loop filter; LOW-POWER; MHZ BANDWIDTH; DB-SNDR; ADC; VOLTAGE; CMOS;
D O I：
10.1109/TCSII.2018.2853088
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This brief presents a 0.6 V third-order continuoustime sigma-delta modulator (CT-SDM) based on single-stage inverter-based amplifiers. The designed amplifier uses an onchip bulk-bias technique to control the common mode output voltage and to mitigate process, voltage and temperature variations. Also, a negative resistance is used at the output of the amplifier to enhance dc gain. To increase power efficiency, a single-amplifier resonator is used in the loop filter. To enable this implementation a compensation technique to mitigate the effects of amplifier's finite dc gain in the resonator transfer function is presented. The proposed CT-SDM was fabricated in a 130-nm CMOS process with an active area of 0.232 mm(2). The modulator achieves a 74.2 dB DR and peak SNDR/SNR of 59.43/69.04 dB for a 100 kHz signal bandwidth while consuming 89.50 mu W from a 0.6-V power supply.
引用
收藏
页码：1310 / 1314
页数：5
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