An analog CMOS double-edge multi-phase low-latency pulse width modulator

This paper presents an analog CMOS double-edge multi-phase low-latency pulse width modulator. The PWM signal is generated by comparing the phase difference between two matched ring oscillators, which are differentially driven by the command voltage and the feedback voltage developed in a minor loop that forces the average frequency of each of the oscillators to be equal. Both rising and falling edges of the PWM signal are controlled by the instantaneous input voltage, resulting in a low latency relative to that achieved with conventional latched PWM circuitry. The developed pulse width modulator has high precision, good linearity, good noise immunity and wide duty ratio range. Further, it can be flexibly reconfigured for multi-phase PWM operation with no restriction on duty cycle range. The complete double-edge pulse width modulator IC is implemented in a 0.18 mu m CMOS process. It can generate as many as sixteen PWM outputs. The active chip area is 0.04 mm(2). The quiescent bias current of the chip is 80 mu A at 1.2 MHz PWM frequency.