High Throughput, Pipelined Implementation of AES on FPGA

被引：23

作者：

Qu, Shanxin ^{[1
]}

Shou, Guochu ^{[1
]}

Hu, Yihong ^{[1
]}

Guo, Zhigang ^{[1
]}

Qian, Zongjue ^{[1
]}

机构：

[1] Beijing Univ Posts & Telecommun, Sch Informat & Telecommun Engn, Beijing 100088, Peoples R China

来源：

IEEC 2009: FIRST INTERNATIONAL SYMPOSIUM ON INFORMATION ENGINEERING AND ELECTRONIC COMMERCE, PROCEEDINGS | 2009年

关键词：

AES; FPGA; Pipelined; GF(2); Throughput;

D O I：

10.1109/IEEC.2009.120

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The FPGA-based high throughput 128 bits AES cipher processor is proposed in this paper. We present an equivalent pipelined AES architecture working on CTR mode to provide the highest throughput up to date through inserting some registers in appropriate points making the delay shortest, when implementing the byte transformation in one clock period. The equivalent pipelined architecture does not change the data stream direction but change the inner process order in round transformation. Xilinx Foundation ISE (TM) 10.1 FPGA design tool is used in the synthesis of the design. And the throughput of 73.737Gbps, clock frequency of 576.07MHz and resource efficiency of 3.21Mbps/LUT are provided by the proposed equivalent pipelined AES architecture. The proposed design reach higher throughput than the other designs up to date, and its resource efficiency is also very high.

引用

页码：542 / 545

页数：4

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