On improving the performance of dynamic positive-feedback source-coupled logic (D-PFSCL) through inclusion of transmission gates

Dynamic positive feedback source-coupled logic (D-PFSCL) gates are used as a low power alternative in mixed signal applications over static positive feedback source coupled logic (PFSCL) gates. In this paper, transmission gates (TG) are included in the dynamic positive-feedback source coupled logic (D-PFSCL) architecture. The proposed scheme allows implementation of logic functions which in existing schemes is restricted to NOR/OR only or three input AND/OR only realization forms. The significant reduction in the number of stages, dynamic current sources and self-timed buffer with proposed scheme leads to efficient D-PFSCL design in comparison to the existing ones. Simulations using PTM 65 nm technology node at frequency of 1 GHz are performed. A maximum improvement of 40.8%, 73% and 97% in delay, dynamic power consumption and EDP respectively is been observed for D-PFSCL exclusive-OR(XOR2) gate implemented using proposed scheme with respect to existing D-PFSCL schemes. Further, a study on the trade-off between power dissipation and frequency of operation is included for the completeness.