New effective algorithm of RAM testing

被引：0
|
作者：
Yarmolik, VN
Mikitjuk, VG
机构：
来源：
AVTOMATIKA I VYCHISLITELNAYA TEKHNIKA | 1996年 / 01期
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
引用
收藏
页码：61 / 71
页数：11
相关论文
共 50 条
  • [31] Testing for effective market supervision of New Zealand banks
    McIntyre, M. L.
    Tripe, David
    Zhuang, Xiaojie
    JOURNAL OF FINANCIAL STABILITY, 2009, 5 (01) : 25 - 34
  • [32] A new scheme for effective IDDQ testing in deep submicron
    Tsiatouhas, Y
    Moisiadis, Y
    Haniotakis, T
    Nikolos, D
    Arapoyanni, A
    2000 IEEE INTERNATIONAL WORKSHOP ON DEFECT BASED TESTING, PROCEEDINGS, 2000, : 9 - 14
  • [33] Compact testing of RAM: Schemes, tools and results
    Bodean, G. C.
    2008 IEEE INTERNATIONAL CONFERENCE ON AUTOMATION, QUALITY AND TESTING, ROBOTICS (AQTR 2008), THETA 16TH EDITION, VOL I, PROCEEDINGS, 2008, : 227 - 232
  • [34] RAM INTERNAL PARALLEL TESTING TECHNIQUE.
    Cady, R.C.
    Furst, R.C.
    Rock, J.E.
    IBM technical disclosure bulletin, 1984, 27 (7 B): : 4534 - 4536
  • [35] Investigation and development of transparent RAM testing principles
    Yarmolik, VN
    Klimets, UV
    van de Goor, A
    AVTOMATIKA I VYCHISLITELNAYA TEKHNIKA, 1997, (06): : 76 - 85
  • [36] A SELF-TESTING DYNAMIC RAM CHIP
    YOU, YG
    HAYES, JP
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (01) : 428 - 435
  • [37] LAB DESIGNS SELF-TESTING RAM
    IVERSEN, WR
    ELECTRONICS-US, 1985, 58 (44): : 22 - 22
  • [38] Testing the interconnect of RAM-based FPGAs
    Renovell, Michel
    Portal, Jean Michel
    Figueras, Joan
    Zorian, Yervant
    IEEE Design and Test of Computers, 1998, 15 (01): : 45 - 50
  • [39] A SELF-TESTING DYNAMIC RAM CHIP
    YOU, Y
    HAYES, JP
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (02) : 508 - 515
  • [40] AN OVERVIEW OF DETERMINISTIC FUNCTIONAL RAM CHIP TESTING
    VANDEGOOR, AJ
    VERRUIJT, CA
    COMPUTING SURVEYS, 1990, 22 (01) : 5 - 33
12345