PDFE: A particle detector front-end asic

This paper describes a low power low noise mixed analog-digital PDFE (particle detector front-end) custom chip developed by IMEC for ESA and intended for scientific energetic particle space born instrumentation (spectroscopy). The ASIC (application-specific integrated circuit) is designed in a standard 0.7-mu m CMOS process. The chip comprises a charge sensitive amplifier, a semi-gaussian pulse-shaping amplifier, a peak detector, a discriminator, an 8-bit ADC and control logic. A second channel is provided for (anti-)coincidence purposes. For cost reasons the circuit is made as versatile as possible by providing several digitally programmable configurations. ENC (equivalent noise charge) is 800e(-)rms at 100pF detector capacitance, 1nA detector leakage and a shaper peaking time of 1 mu s. Conversion gain is 30mV/fC and full scale input is 0.1pC. Power consumption is 50mW when all blocks are enabled; power supply is 5V. The die area measures 31mm(2). A baseline shift of 15mV is realised at 250Ksamples/s (this is the maximum counting rate) for inputs limited to 2.5fC and at 25Ksamples/s for full scale inputs. Radiation hardness is implemented both at the transistor level and at the architectural level. Table 1 lists the main specifications.