Automated Generation of Dynamic Binary Translators for Instruction Set Simulation

被引：0

作者：

Okuda, Katsumi ^{[1
]}

Yoshida, Minoru ^{[1
]}

Takeyama, Haruhiko ^{[1
]}

Nakamura, Minoru ^{[1
]}

机构：

[1] Mitsubishi Electr Corp, Adv Technol R&D Ctr, Tokyo, Japan

来源：

2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) | 2017年

关键词：

DESCRIPTION LANGUAGE;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Instruction set simulators (ISSs) are indispensable tools for developing new architectures and embedded software. Due to the increasing variety of architectures and time-to-market pressure, it is important to efficiently develop fast ISSs based on dynamic binary translation. However, the implementation of such ISSs needs more effort than interpretive ISSs. In this paper, we propose a novel framework that generates ISSs based on dynamic binary translation from descriptions of interpretive ISSs. Our results on SH, MIPS64, and ARM show that the generated ISSs are 1.4 to 13.4 times faster than their original interpretive ISSs.

引用

页码：214 / 219

页数：6

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