A low power, high SFDR, ROM-Less direct digital frequency synthesizer

被引：0
|
作者：
Jafari, H. [1 ]
Ayatollahi, A. [1 ]
Mirzakuchaki, S. [1 ]
机构：
[1] Iran Univ Sci & Tech, EE Dept, Tehran, Iran
来源：
2005 IEEE CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, PROCEEDINGS | 2005年
关键词：
direct digital frequency synthesizer (DDFS); frequency synthesizer; ROM-less;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes the design of a ROM-Less Direct Digital Frequency Synthesizer. The Spurious Free Dynamic Range (SFDR) of the proposed DDFS system is -91.51dBc. A DDFS IC has been designed in HP 0.5 mu m standard N-Well CMOS process technology, and that's layout has 2.489mm(2) area. A 32-bit frequency control word gives a tuning resolution of 0.023Hz at 100MHz sampling rate. This DDFS consume 60mW with 3.3-V supply at 100MHz, and correctly operates up 106MHz.
引用
收藏
页码：829 / 832
页数：4
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