A low-power reduced-area ROM architecture for cryptographic algorithms

This paper describes a new low-power, reduced-area, ROM architecture for block cipher applications. It exhibits a small speed penalty compared to a more conventional ROM implementation, but has the additional advantage of scalability. Area optimization is achieved by using a single decoder, a single set of input and output circuits, a single timing and control module, but a (variable) number of programmable ROM core blocks. A small logic block, which has an insignificant area overhead, is used to select the appropriate ROM core. This approach achieves a 3 to 5-fold area savings as compared to a previous ROM structure described by Mckinney [1]. Additionally, the area saving increases as the required ROM size increases.