Design and modelling of a nonblocking input-buffer ATM switch

In this paper, we introduce a new ATM switch architecture. Buffer access speeds of the proposed architecture match the port speeds, and the buffer acts, in effect, as a multiport memory. The input buffers are implemented as a group of parallel shift registers. This approach overcomes the head-of-the-line (HOL) and low-throughput problems of input buffers. Shift-register buffers allow operating speeds much higher than are possible using RAM buffers. Furthermore, switch speed is independent of buffer size. This is a very important feature for ATM networks that require storage of large amounts of cells in the switching nodes. The parallel nature of the input queues allows for multicast functions. In addition, the modularity of the proposed architecture facilitates its scalability. A dispatching mechanism for cell selection in ATM switches with multiple priorities is also introduced. The proposed switching scheme satisfies real-time and nonreal-time quality-of-service (QoS) requirements. Simulations of the switch with the new dispatching mechanism are performed under a diversity of bursty traffic loads.