Energy reduction opportunities in Field-Coupled Nanocomputing Adders

According to the International Roadmap for Devices and Systems, Field-Coupled Nanocomputing devices and reversible computing techniques are promising topics in a beyond CMOS scenario. In this work, we investigate the application of both subjects in Adders. Precisely, we analyze the energy reduction opportunities in FCN classical Adder's topologies (i. e., ripple carry, carry lookahead, and carry lookahead block), applying state-of-the-art partially reversible techniques to them. Our goal is to understand the association between the density of connections and logic gates and the achievable fundamental energy limit reduction. We found that, despite the significant differences in depth and size between the topologies, applying the techniques, their fundamental energy limits are almost the same. Moreover, when energy is a critical concern, energy limits could be reduced by up to 54%.