Design of Accurate Low-Cost On-Chip Structures for Protecting Integrated Circuits Against Recycling

被引:41
|
作者
Guin, U. [1 ]
Forte, D. [2 ]
Tehranipoor, M. [2 ]
机构
[1] Univ Connecticut, Dept Elect & Comp Engn, Storrs, CT 06269 USA
[2] Univ Florida, Dept Elect & Comp Engn, Gainesville, FL 32611 USA
基金
美国国家科学基金会;
关键词
Combating die and IC recycling (CDIR); counterfeit integrated circuits (ICs); negative bias temperature instability (NBTI)-aware; recycling; SILICON ODOMETER; NBTI; HCI;
D O I
10.1109/TVLSI.2015.2466551
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The recycling of electronic components has become a major industrial and governmental concern, as it could potentially impact the security and reliability of a wide variety of electronic systems. It is extremely challenging to detect a recycled integrated circuit (IC) that is already used for a very short period of time because the process variations outpace the degradation caused by aging, especially in lower technology nodes. In this paper, we propose a suite of solutions, based on lightweight negative bias temperature instability (NBTI)-aware ring oscillators (ROs), for combating die and IC recycling (CDIR) when ICs are used for a very short duration. The proposed solutions are implemented in the 90-nm technology node. The simulation results demonstrate that our newly proposed NBTI-aware multiple pair RO-based CDIRs can detect ICs used only for a few hours.
引用
收藏
页码:1233 / 1246
页数:14
相关论文
共 50 条
  • [41] AN INTEGRATED DESIGN PROCESS OF LOW-COST HOUSING IN CHILE
    Trebilcock-Kelly, Maureen
    Saelzer-Fica, Gerardo
    Bobadilla-Moreno, Ariel
    JOURNAL OF GREEN BUILDING, 2019, 14 (03): : 81 - 93
  • [42] Impact of on-chip inductance on power distribution network design for nanometer scale integrated circuits
    Srivastava, N
    Qi, XN
    Banerjee, K
    6TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2005, : 346 - 351
  • [43] Integrated test data decompression and core wrapper design for low-cost system-on-a-chip testing
    Gonciari, PT
    Al-Hashimi, BM
    Nicolici, N
    INTERNATIONAL TEST CONFERENCE 2002, PROCEEDINGS, 2002, : 64 - 73
  • [44] Design and analysis of on-chip tapered transformers for silicon radio-frequency integrated circuits
    Cho, MH
    Chen, KM
    Huang, GW
    Chiu, CS
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2005, 44 (4B): : 2166 - 2170
  • [45] Design and analysis of on-chip tapered transformers for silicon radio-frequency integrated circuits
    Cho, Ming-Hsiang
    Chen, Kun-Ming
    Huang, Guo-Wei
    Chiu, Chia-Sung
    Jpn J Appl Phys Part 1 Regul Pap Short Note Rev Pap, 4 B (2166-2170):
  • [46] A new design methodology using simulation for on-chip ESD protection designs for integrated circuits
    Wang, AZ
    Tsay, CH
    1998 5TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY PROCEEDINGS, 1998, : 509 - 512
  • [47] PRACTICAL DESIGN OF LOW-COST LARGE SPACE STRUCTURES
    HEDGEPETH, JM
    MIKULAS, MM
    MACNEAL, RH
    ASTRONAUTICS & AERONAUTICS, 1978, 16 (10): : 30 - 34
  • [48] Multimedia training on integrated circuits design with low cost hardware
    Casanueva, R
    Azcondo, FJ
    Martinez, M
    Bracho, S
    MICROELECTRONICS EDUCATION, 1998, : 273 - 276
  • [49] FEATHER: A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
    Tong, Jianming
    Itagi, Anirudh
    Chatarasi, Prasanth
    Krishna, Tushar
    2024 ACM/IEEE 51ST ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, ISCA 2024, 2024, : 198 - 214
  • [50] Low-cost fabrication of an on-chip Fabry-Perot interferometer for dry environmental monitoring
    Guertin, Regis
    Bianki, Marc-Antoine
    Peter, Yves-Alain
    2023 INTERNATIONAL CONFERENCE ON OPTICAL MEMS AND NANOPHOTONICS, OMN AND SBFOTON INTERNATIONAL OPTICS AND PHOTONICS CONFERENCE, SBFOTON IOPC, 2023,