MemTracker: Efficient and programmable support for memory access monitoring and debugging

被引:0
|
作者
Venkataramani, Guru [1 ]
Roemer, Brandyn [1 ]
Solihin, Yan [2 ]
Prvulovic, Milos [1 ]
机构
[1] Georgia Tech, Atlanta, GA USA
[2] North Calif State Univ, Raleigh, NC USA
基金
美国国家科学基金会;
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Memory bugs are a broad class of bugs that is becoming increasingly common with increasing software complexity, and many of these bugs are also security vulnerabilities. Unfortunately, existing software and even hardware approaches for finding and identifying memory bugs have considerable performance overheads, target only a narrow class of bugs, are costly to implement, or use computational resources inefficiently. This paper describes MemTracker, a new hardware support mechanism that can be configured to perform different kinds of memory access monitoring tasks. MemTracker associates each word of data in memory with a few bits of state, and uses a programmable state transition table to react to different events that can affect this state. The number of state bits per word, the events to which MemTracker reacts, and the transition table are all fully programmable. MemTracker's rich set of states, events, and transitions can be used to implement different monitoring and debugging checkers with minimal performance overheads, even when frequent state updates are needed. To evaluate MemTracker, we map three different checkers onto it, as well as a checker that combines all three. For the most demanding (combined) checker, we observe performance overheads of only 2.7% on average and 4.8% worst-case on SPEC 2000 applications. Such low overheads allow continuous (always-on) use of MemTracker-enabled checkers even in production runs.
引用
收藏
页码:273 / +
页数:2
相关论文
共 50 条
  • [1] MemTracker: An Accelerator for Memory Debugging and Monitoring
    Venkataramani, Guru
    Doudalis, Ioannis
    Solihin, Yan
    Prvulovic, Milos
    ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 2009, 6 (02)
  • [2] Memory-Efficient Performance Monitoring on Programmable Switches with Lean Algorithms
    Liu, Zaoxing
    Zhou, Samson
    Rottenstreich, Ori
    Braverman, Vladimir
    Rexford, Jennifer
    SYMPOSIUM ON ALGORITHMIC PRINCIPLES OF COMPUTER SYSTEMS, APOCS, 2020, : 31 - 44
  • [3] iWatcher: Efficient architectural support for software debugging
    Zhou, P
    Qin, F
    Liu, W
    Zhou, YY
    Torrellas, J
    31ST ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, PROCEEDINGS, 2004, : 224 - 235
  • [4] Efficient Implementation of 2-D FCT with Reduced Memory Access for Programmable DSPs
    Liu, Xiangyang
    Bao, Hua
    JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2015, 80 (02): : 153 - 161
  • [5] Efficient Implementation of 2-D FCT with Reduced Memory Access for Programmable DSPs
    Xiangyang Liu
    Hua Bao
    Journal of Signal Processing Systems, 2015, 80 : 153 - 161
  • [6] A VIRTUAL MEMORY MANAGEMENT CHIP WITH PROGRAM DEBUGGING SUPPORT
    LAVI, Y
    MIZRACHI, A
    ISSCC DIGEST OF TECHNICAL PAPERS, 1983, 26 : 26 - 27
  • [7] Interconnect support for energy efficient and high bandwidth memory access in CMPs
    Mondal, Hemanta Kumar
    Konar, Sarnava
    Hore, Poulomi
    Patra, Ramapati
    Sarkar, Pradipta
    Deb, Sujay
    SUSTAINABLE COMPUTING-INFORMATICS & SYSTEMS, 2022, 34
  • [8] Organization and application of the programmable ordered access memory
    Melnyk, Anatoliy
    al Ravashdech, Dzavad
    al Hababsach, Mohammad
    EXPERIENCE OF DESIGNING AND APPLICATION OF CAD SYSTEMS IN MICROELECTRONICS, 2009, : 240 - 241
  • [9] AntSM: Efficient Debugging for Shared Memory Parallel Programs
    Lee, Jae-Woo
    Midkiff, Samuel P.
    LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING, LCPC 2013, 2014, 8664 : 202 - 216
  • [10] ASeD: Availability, Security, and Debugging Support using Transactional Memory
    Chung, JaeWoong
    Baek, Woongki
    Bronson, Nathan Grasso
    Seo, Jiwon
    Kozyrakis, Christos
    Olukotun, Kunle
    SPAA'08: PROCEEDINGS OF THE TWENTIETH ANNUAL SYMPOSIUM ON PARALLELISM IN ALGORITHMS AND ARCHITECTURES, 2008, : 366 - 366