Delay time estimation model for large digital CMOS circuits

Delay time estimation in simulation or design verification step during a design cycle has become more and more important as the meaning of performance prediction. This paper proposed a delay estimation model for digital CMOS circuits, which works in gate-level but the modeling process includes the characteristics of MOSFETs. This model can handle the variation according to the kind of gates, input transition time, output load(fan-out), and transistor sizes of a gate. The procedure to find the general model was that, a delay model for CMOS inverter was extracted first, then it was extended to other gate by converting it into an equivalent inverter. The resulting model was evaluated and compared with SPICE simulation, which showed that the proposed model has the accuracy of less than 5% relative error rate to the SPICE results for each case and the speed of about 70 times faster than SPICE.