A variable-radix digit-serial design methodology and its application to the discrete cosine transform

被引：6

作者：

Leong, MP ^{[1
]}

Leong, PHW ^{[1
]}

机构：

[1] Chinese Univ Hong Kong, Dept Syst & Comp Engn, Shatin, Hong Kong, Peoples R China

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2003年 / 11卷 / 01期

关键词：

design automation; design methodology; discrete cosine transforms; field-programmable gate arrays (FPGAs); fixed-point arithmetic;

D O I：

10.1109/TVLSI.2003.811099

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A variable-radix digit-serial design methodology and its application to the implementation of a systolic structure for computing the discrete cosine transform is presented. Based on the parameters supplied by a user, different fixed-point designs can be derived from a single floating-point description where tradeoffs among quantization effects, throughputs latency, and area can be addressed. The resulting hardware implementations have variables of different wordlengths and operators of different radices. This design methodology enables efficient exploration of a complex design space to determine the most suitable implementation for a particular application.

引用

页码：90 / 104

页数：15