Dynamic threshold voltage MOSFETs for future low power sub 1V CMOS applications

被引：0

作者：

Suryagandh, SS ^{[1
]}

Anand, B ^{[1
]}

Desai, MP ^{[1
]}

Rao, VR ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect Engn, Bombay 400076, Maharashtra, India

来源：

PROCEEDING OF THE TENTH INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES, VOLS I AND II | 2000年 / 3975卷

关键词：

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Threshold voltage scaling in deep sub-micron CMOS technologies is often dictated by the allowable off-state leakage currents and power dissipation. A recently proposed novel operation of a MOSFET is discussed in this paper, which is suitable for ultra low voltage operation (0.6 V or below) of ULSI circuits. In this mode of operation (referred to as Dynamic Threshold Voltage MOS, DTMOS), threshold voltage is made a function of gate voltage by tying the gate to the substrate of the MOSFET. Extensive comparisons are made in this work, using detailed device and circuit level simulations, on bulk DTMOS and conventional MOS structures. Our results show substantially higher drive currents and speeds for DTMOS operation, in comparison to the conventional MOSFET circuits, when the supply voltage is scaled below 1 V in the deep submicron technologies.

引用

页码：655 / 658

页数：4

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