Etching high aspect ratio silicon trenches

被引：0

作者：

Panda, S ^{[1
]}

Ranade, R ^{[1
]}

Mathad, GS ^{[1
]}

机构：

[1] IBM Microelect, Semicond Res & Dev Ctr, Hopewell Jct, NY 12533 USA

来源：

PLASMA PROCESSING XIV | 2002年 / 2002卷 / 17期

关键词：

D O I：

暂无

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

High aspect ratio trenches are necessary to achieve target values of capacitance in the fabrication of charge storage capacitors in DRAM devices. Etching of high aspect ratio trenches suffers from a RIE lag mechanism, due to reduced energy of ions and etching species at the bottom of a deep trench. In this paper, two methods are proposed to minimize these problems and thereby achieve higher silicon etch rates and deeper trenches.

引用

页码：210 / 217

页数：8

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