FEERIC, a very-front-end ASIC for the ALICE Muon Trigger Resistive Plate Chambers

The ALICE Collaboration at the CERN-LHC has started a vast program of upgrades in the context of the increase of the luminosity of the LHC from 2018 on. The present very front-end electronics (VFE) of the Muon Trigger, whose acronym is ADULT, must be replaced to prevent the aging of the Resistive Plate Chamber (RPC) detector in the future expected operating conditions. The new VFE, FEERIC (Front-End Electronics Rapid Integrated Circuit), will have to perform amplification of the analog input signal (this is not the case for ADULT). This will allow for RPC operation in a low-gain avalanche mode, with a much smaller (factor 3-5) charge deposit in the detector with respect to the present conditions. The purpose is to discriminate RPC signals with a charge threshold around 100 fC, in both polarities. The VFE system consists of 21,000 channels, distributed over 2400 electronics cards equipped with one or two ASICs. A total of 3000 ASICs of 8 channels each is necessary. The future ASIC has to insure mainly the following functions: amplification, discrimination and LVDS output stage. FEERIC will be capable of handling bipolar signals varying from +/- 20 fC up to +/- 3 pC with a fixed threshold of typically 100 fC. A prototype chip has been designed using the 0.35 mu m CMOS technology of AMS. The time resolution is less than 500 ps rms for an input charge of +/- 100 fC. The time resolution is 30 ps rms for an input charge of +/- 3 pC. The cross-talk is less than 2% for an input charge of +/- 3.5 pC and a threshold of +/- 20 mV (corresponding to approximate to 70 fC). The global power consumption per channel is 60 mW, with a 3 V power supply.