Dimensional effects on the reliability of polycrystalline silicon thin-film transistors

被引:1
|
作者
Zan, HW
Shih, PS
Chang, TC
Chang, CY
机构
[1] Natl Chao Tung Univ, Inst Elect, Hsinchu, Taiwan
[2] Natl Nano Devices Labs, Hsinchu 300, Taiwan
[3] Natl Sun Yat Sen Univ, Dept Phys, Kaohsiung, Taiwan
关键词
D O I
10.1016/S0026-2714(00)00165-7
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We found that for unpassivated short-channel TFTs, hot carrier stress-induced degradation phenomena are different with various channel geometries. For device with a wide channel width, the threshold voltage is increased while the subthreshold swing is almost unchanged. The stress-induced oxide-trapped charges are responsible for the degradation. For others with narrow channel widths after stress, on the contrary, the subthreshold swing and I-min are increased, the trap density is greatly increased and the trap-enhanced kink effect is also observed. This is due to the generation of stress-induced grain boundary traps near the drain side. Additionally, the stress-induced degradations of passivated TFTs with various geometries are identical. The increased defect density dominates the mechanism since the hot-carrier stress tends to break the passivated SI-H bonds. (C) 2000 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码:1479 / 1483
页数:5
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